InertialWave ASIC engineer Vladimir Vesely will present his research on a novel time-domain ADC architecture, the PLL-SAR, at the 2023 Midwest Symposium on Circuits and Systems in Pheonix, AZ. This paper was based on research performed during his time at Oregon State University, and will be published under the name “PLL-SAR: A New High-Speed Analog to Digital Converter Architecture”.



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